The present invention relates to an inverter apparatus in which the suppression of an excess current is intensified when an induction motor is to be driven by V/f control.
Conventionally, a current is increased if a rapid acceleration is carried out or a load is suddenly changed when the induction motor is to be V/f controlled. In that case, when a current exceeding a tolerance flows to the semiconductor device of an inverter apparatus, the device is broken down. Consequently, an excess current level is set. When a current exceeding the excess current level flows, an excess current protecting function is fulfilled to prevent the breakdown of the device by gate breaking.
Referring to the gate breaking fulfilled by the excess current protecting function, moreover, restarting is required. For this reason, a current is limited and a semiconductor is protected by using a gate breaking circuit having the function of carrying out an automatic reset at a lower level than a previous excess current level or a current limiting circuit for outputting a 0 voltage pattern to a much lower level.
Furthermore, there has been performed control for paying attention to only the magnitude of a current, for example, a method of detecting the magnitude of a current to correct a frequency, and a method of stopping an acceleration if the current is increased during the acceleration and reducing a frequency if the current is increased during a stationary operation.
Next, description will be given to a specific example in which conventional V/f control is actually carried out.
FIG. 5 is a control block diagram showing the conventional V/f control. FIG. 8 shows an example of a voltage command Vq* and a current I in a certain power state in the V/f control shown in FIG. 5, and a voltage component of an electric motor, in which an axis d indicates a reference phase of a control output, illustrating a control configuration for controlling a voltage of an axis q set into a position at 90 degrees from the axis d.
In the V/f control shown in FIG. 5, xcex8represents a position of the axis d seen from a certain reference position (for example, a U phase). A frequency command calculating section 1 inputs a frequency command Fref and calculates an acceleration frequency from an acceleration time set by acceleration command calculating means 2, and integrates the acceleration frequency by acceleration frequency integrating means 3, stops an acceleration when a frequency command value set by command value limiting means 4 is obtained, and thus creates a frequency command at the present time.
Moreover, when a speed integrated by the acceleration frequency integrating means 3 is set to have a lower limit value to be a frequency command value by the command value limiting means 4 during a deceleration, the deceleration is stopped. Slip frequency means 5 calculates the slip frequency of an electric motor from a current detection value for a torque, thereby obtaining an output frequency 6.
A V/f calculating section 7 obtains the voltage command Vq* from the output frequency based on a frequencyxe2x80x94voltage pattern shown in FIG. 7. Moreover, the output frequency is integrated by phase calculating means 8 to obtain an output phase xcex8, and a three-phase (UVW phase) voltage command is obtained from voltage commands Vq* and Vd* (a value of 0) and xcex8 by a PWM command calculating section 9 and is converted into a PWM pattern, and the PWM pattern is output to a gate driver circuit 10 and a voltage is applied to an electric motor 1M.
Conventionally, a magnitude I1 of a current is detected by current detecting means 12b as stall (stop state) preventing measures, and an acceleration is delayed if any and the acceleration (deceleration) is carried out with a negative value during a stationary operation when the magnitude I1 is increased by acceleration correcting means 11b. In some cases in which a rapid acceleration is carried out or a load fluctuates suddenly, however, an increase in the current cannot be suppressed so that a stall is carried out due to the excess current protection of hardware.
For this problem, there are taken measures for creating a current limiting circuit shown in FIG. 6 to control a current, thereby preventing the stall.
As shown in FIG. 6, the current limiting circuit is added to an ordinary structure in which a conversion into a voltage having a UVW phase is carried out from the dq axes by voltage converting means 9a in the PWM command calculating section 9 and a PWM modulation is carried out over the same voltage by a triangular wave comparator 9b, and a gate drive signal is thus created through an inverting circuit and a non delay circuit 26. Consequently, the breakdown of a semiconductor device can be prevented. In the drawing, an excess current level is divided into three stages of:
Ioc greater than Ic1b greater than Ic1a, and
a current detection value I1 is first compared with an excess current level Ioc by a comparator 21. When I1 is greater than Ioc, the result of the comparison is latched into a latch circuit 24 and a gate breaking signal is selected and output by a gate breaking selection circuit 27. The latch circuit 24 is reset in response to a reset signal sent from a controller in a predetermined timing.
If a current is smaller, a result obtained by comparing the current detection value I1 with a next current limitation level Iclb by a comparator 20 is latched into a latch circuit 23 and a gate breaking signal is output by the gate breaking selection circuit 26. The comparator 20 and the latch circuit 23 will be referred to as a CLB circuit.
If the current is further smaller, the current detection value I1 is compared with a subsequent current limitation level Ic1a by a comparator 19. If I1 is greater, an on signal is latched into a latch circuit 22 and is sent to a 0 voltage switching circuit 25, and a 0 voltage pattern created by a 0 voltage pattern generator 18 is output. The comparator 19 and the latch circuit 22, and the 0 voltage pattern generating circuit 18 and the 0 voltage switching circuit 25 will be generally referred to as a CLA circuit.
The latch circuits 22 and 23 are automatically reset in a certain set timing CLK. Consequently, in the case in which the current detection value I1 is smaller than the excess current level Ioc and is greater than the current limitation level Ic1a, a gate drive signal having a fixed pattern is obtained. However, since gate breaking is not carried out, it is possible to continuously perform the operation while limiting the current. In the excess current preventing measures to be taken depending on only the magnitude of a current, the current is increased if a voltage is dropped in the regeneration state of an electric motor, and furthermore, a power is not supplied to the electric motor while the CLA and CLB circuits are operated. For this reason, it cannot be denied that an efficiency is reduced.
Examples of a method other than the correction to be carried out depending on the magnitude of a current include a method of correcting a voltage by using a voltage limitation vector in a reverse direction to the magnitude of a detected current and PI controlling the magnitude of the voltage limitation vector, thereby correcting a speed command.
In the case of the method in FIG. 6, however, the magnitude of the voltage is corrected from the magnitude of the current to carry out a current limitation. Therefore, if the voltage is reduced when the electric motor is set in a regeneration state, the current is increased. Thus, the current cannot be limited depending on the state of the electric motor but is increased so that the excess current protecting function is fulfilled and a stall is caused by gate breaking in some cases.
In a method using a 0 voltage, moreover, a current is distorted so that the supply of a power to the electric motor is eliminated. As a result, the efficiency is reduced. For this reason, there is a problem in that the demand has not been met though a current limiting method having a high power efficiency is desired while a current is reliably dropped.
Furthermore, in the case in which a voltage is corrected by using a voltage limitation vector in a reverse direction to a detected current and PI control is carried out over the voltage limitation vector to correct a speed command, it is possible to decrease a current by compensating for a voltage with the vector in the reverse direction to the current. In the case in which the electric motor is set in a power state in order to carry out, over the speed command, the PI control for paying attention to only the magnitude of the current, the correction is carried out. In some cases of regeneration, the frequency correction has a bad influence and the current cannot be limited. Moreover, the PI control is used for a speed correcting method. In the case in which a great load is instantaneously applied, therefore, a great frequency correction corresponding thereto is carried out so that an unstable state is apt to be brought. Furthermore, there is a danger that the integration might be accumulated to cause runaway in the stable condition. The correction is performed in the directions of voltage corrections DVq and DVd which are not restricted to a voltage control axis direction but include a direction orthogonal thereto. For this reason, there is a problem in that it is hard to suppress the generation of a drawback such as hunting and a stability cannot be maintained.
Accordingly, it is an object of the invention to provide an inverter apparatus capable of reliably limiting a current to prevent the breakdown of a device and a stall irrespective of the state of an electric motor, thereby operating the electric motor efficiently and stably, and a current limiting method thereof.
In order to attain the object, the invention provides (1) an inverter apparatus for obtaining a voltage command vector from a frequency command value and a voltage command value calculated by a V/f operation based on the frequency command value, and carrying out a PWM modulation based on the voltage command vector, thereby outputting a voltage, comprising current detecting means for detecting a current vector having a magnitude of a current and a current phase, voltage limitation value calculating means for calculating a voltage limitation value which is proportional to an excess when the magnitude of the current exceeds a current limitation value, voltage limitation vector calculating means for converting the voltage limitation value into a voltage limitation vector based on the current phase, voltage correcting means for adding the voltage limitation vector to the voltage command vector, and acceleration correcting means for correcting an acceleration command of a frequency based on the voltage limitation value and the current phase.
Moreover, the invention is characterized in that (2) the voltage limitation value calculating means outputs, as a voltage limitation value, a result obtained by filtering a value proportional to an excess by means of a first order time-lag filter when the current limitation value is exceeded.
Furthermore, the invention is characterized in that (3) the voltage limitation vector calculating means converts the voltage limitation value into a vector in a reverse direction to the current phase.
Moreover, the invention is characterized in that (4) the voltage limitation vector calculating means calculates the voltage limitation value of a voltage limitation vector by setting, to zero, a component of the vector in the reverse direction to the current phase which is orthogonal to the voltage command vector direction.
Furthermore, the invention is characterized by (5) second current limiting means for forcibly outputting a PWM pattern of a zero voltage while a magnitude of a current exceeds a second current limitation value which is greater than the current limitation value, and third current limiting means for breaking a gate while the magnitude of the current exceeds a third current limitation value which is greater than the second current limitation value.
Moreover, the invention is characterized by (6) means for invalidating a function for the second current limiting means and the third current limiting means.
Furthermore, the invention is characterized by (7) a current limiting method of an inverter apparatus for obtaining a voltage command vector from a frequency command value and a voltage command value calculated by a V/f operation based on the frequency command value, carrying out a PWM modulation based on the voltage command vector, thereby outputting a voltage, and performing a protecting operation when an excess current is detected, comprising the steps of detecting a current vector including a magnitude Il of a current and a current phase xcex8i, calculating a voltage limitation value xcex94V which is proportional to an excess when the magnitude of the current exceeds a current limitation value Imax, converting the voltage limitation value xcex94V into voltage limitation vectors xcex94Vq and xcex94Vd based on the current phase xcex8i, adding them to the voltage command vector to carry out a voltage correction, thereby limiting the current instantaneously, and correcting an acceleration command of a frequency based on the voltage limitation value and the current phase, thereby carrying out a current limitation having a high power efficiency.
Moreover, the invention is characterized in that (8) the voltage limitation value xcex94V is output by filtering a value proportional to an excess by means of a first order time-lag filter and removing higher harmonics when the magnitude of the current exceeds a current limitation value Imax.
Furthermore, the invention is characterized in that (9) the voltage limitation vectors xcex94Vq and xcex94Vd are created by converting the voltage limitation value xcex94V into a vector xcex94Vq
=xe2x88x92xcex94Vsinxcex8i (or xcex94Vq=xe2x88x92xcex94Vxc3x97Iq/Il) and a vector xcex94Vd=xe2x88x92xcex94Vcosxcex8i (or xcex94Vd=xe2x88x92xcex94Vxc3x97Id/Il) in a reverse direction to the current phase xcex8i.
Moreover, the invention is characterized in that (10) the voltage limitation value xcex94V of the voltage limitation vector is obtained by setting, to zero, a Ad component of the vectors xcex94q and xcex94d in the reverse direction to the current phase xcex8i which is orthogonal to the voltage command vector direction.
Furthermore, the invention is characterized by (11) the steps of forcibly outputting a PWM pattern of a zero voltage while the magnitude of the current exceeds a second current limitation value Iclaxe2x80x2 which is greater than the current limitation value Imax, and breaking a gate while the magnitude of the current exceeds third current limitation values Iclbxe2x80x2 and Iocxe2x80x2 which are greater than the second current limitation value Iclaxe2x80x2.
Moreover, the invention is characterized in that (12) a protection function based on the second and third current limitation values can be invalidated.
According to the inverter apparatus and the excess current suppressing method thereof, the voltage limitation value xcex94V which is proportional to the excess of the excess current limitation value Imax in FIG. 1 is obtained and is converted into the voltage limitation vectors xcex94Vq and xcex94Vd based on the current phase, and the voltage limitation vectors xcex94Vq and xcex94Vd are added to the voltage command vector. Consequently, the excess current can be suppressed instantaneously. In addition, the acceleration command of the frequency is corrected based on the voltage limitation value xcex94V and the current phase xcex8i. Consequently, it is possible to avoid a stall and to efficiently carry out an operation while limiting a current.
In that case, the voltage limitation value xcex94V is caused to pass through a first order time-lag filter (K/1+Ts) and the voltage limitation vector is then obtained. Consequently, it is possible to carry out a stable compensation from which a high harmonic component included in a current is removed.
Moreover, when the voltage limitation value xcex94V is to be converted into the voltage limitation vectors xcex94Vq and xcex94Vd, the voltage limitation vector is obtained in a reverse direction to a direction of a current and a compensation is thus carried out. Consequently, it is possible to instantaneously limit a current for the use such as a resistance load. In the case in which a motor is to be controlled, moreover, the direction component xcex94Vd which is orthogonal to the voltage command vector in the component of the voltage limitation vector in the reverse direction to the current is set to be zero, and only the direction of the voltage command vector to be V/f controlled is thus compensated. Consequently, stable current limitation control can be carried out.
As a measure for protection in the case in which the current limitation is not carried out normally, the PWM pattern of a zero voltage is forcibly output to carry out a protecting operation while the magnitude I1 of the current exceeds the second excess current limitation value Iclaxe2x80x2 which is greater than the excess current limitation value Imax, and the gate is broken and protected while the magnitude I1 of the current exceeds the third excess current limitation value Iclbxe2x80x2 or Iocxe2x80x2 which is greater than the second excess current limitation value Iclaxe2x80x2. Even if the magnitude I1 the current greatly exceeds the excess current limitation value Imax, consequently, the second and third excess current limitation values Iclaxe2x80x2, Iclbxe2x80x2 and Iocxe2x80x2 are protected in three stages. Therefore, it is possible to suppress an excess current reliably and safely. In this case, the relationship between the set levels of Iocxe2x80x2  greater than Iclbxe2x80x2 greater than Iclaxe2x80x2 greater than Imax is obtained.
In the invention, accordingly, the suppression can be carried out almost completely based on the excess current limitation value Imax. Therefore, it is possible to increase the values of the set levels Ioc, Iclb and Icla of CLA and CLB circuits having excess current levels set in the conventional case.
Moreover, the control of the excess current limitation value Imax is almost enough. Therefore, switching means 29a and 29b for invalidating the CLA and CLB circuits are provided such that the CLA and CLB circuits can be turned ON/OFF. Thus, the control can be carried out widely.